Design of High speed Vedic MAC Unit using Urdhva Tiryakbhyam sutra & comparison with Conventional Architecture Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Arpita A. Koli, S.B. Kulkarni Subject(s): Engineering, Applied Linguistics
Implementation of Modified Booth Algorithm for Parallel MAC Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Stephen Last Name, Ravikumar. M Subject(s): Engineering, Applied Linguistics
A Review on Multiplier Circuits based on Various Performance Parameters Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: R. Alwin, Dr. R. Naveen Subject(s): Engineering, Applied Linguistics
Design of Parallel MAC Based On Radix-4 & Radix-8 Modified Booth Algorithm Journal title: International Journal of Research in Computer and Communication Technology Authors: S. Anitha, M. Vidya, D. Mahesh Varma Subject(s): Computer and Information Science, Telecommunications
A New VLSI Architecture to Increase the speed of computation (Modified Booth Algorithm) Journal title: International Journal of Research in Computer and Communication Technology Authors: CH.Rama Koti Reddy, K. Satyavathi, R.Raja Kishore Subject(s): Computer and Information Science, Telecommunications
32 Bit Parallel Multiplier Using VHDL Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey Subject(s):
An Efficient Baugh-WooleyArchitecture forBothSigned & Unsigned Multiplication Journal title: International Journal of Computer Science & Engineering Technology Authors: PramodiniMohanty , RashmiRanjan Subject(s):
Design of RNS Based Addition Subtraction and Multiplication Units Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: N Vivek , K Anusudha Subject(s):
Design and Analysis of Hybrid Tree Multipliers for Reduction of Partial Products Journal title: Mehran University Research Journal of Engineering and Technology Authors: S. Bibi, M. Obaidullah, M.A. Shami Subject(s):
Review on Multiply-Accumulate Unit Journal title: International Journal of engineering Research and Applications Authors: Roshani Pawar, Dr. S. S. Shriramwar Subject(s):
High Speed Arithmetic: Interleaved Modular Multipliers Using Radix 8 Booth Encoder Journal title: IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) Authors: Deepthi R Shetty, Ashwath Rao, Praveen Kumar M Subject(s):
